A liquid crystal display device, as a dot matrix display device, is used in a variety of devices, such as personal computers, because of its meritorious features, such as thin thickness, small light and low power consumption, In particular, the active matrix color liquid crystal display device now forms the mainstream in that it lends itself to control of the picture quality to extremely high definition.
A liquid crystal display module of a liquid crystal display device includes a liquid crystal panel (LCD panel), a control circuit, referred to below as a controller, and made up by a semiconductor integrated circuit device, referred to below as an IC, a scanning side driving circuit, formed by the IC, and a data side driving circuit, referred to below as a data driver. A plural number of data drivers are used. For example, in a case where the resolution of a liquid crystal panel is XGA (1024×768 pixels, each pixel being composed of three dots of R (red), G (green) and B (blue)), there being 262144 display colors, each of R, G and B being of 64 gradations, eight data drivers are used, when it is assumed that each data driver takes charge of 128 pixels.
Each data driver includes a shift register and a data register for converting serial data into parallel data and for capturing the so converted data. The shift register is responsive to a start signal to output, at a data register, a control signal for capturing 128 pixels, sequentially shifted in synchronism with clock signals. The start signal is entered from the controller to the first stage data driver and sequentially transmitted to second and following data drivers, interconnected in cascade, such that the eight data drivers operate as a sole shift register. In the case of a parallel transmission system, capturing display data with a bit width corresponding to two pixels, two pixels of display data are captured with one control signal. Thus, the shift register of each data driver has to output 64 control signals, and hence 64 stages of flip-flops are connected to one another in cascade. In this case, the start signal for the next stage of the cascade-connected next-stage data driver is not output from the 64th stage flipflop but an output of e.g. the 62nd flipflop is delivered via a start signal output circuit. On the other hand, clock signals are entered to the shift register via a clock signal input/output circuit having a clock stop circuit (for example, see JP Patent Kokai Publication No. JP-A-9-281924).